Conventionally, memory devices of the type comprising a memory plane, that is, a matrix of memory cells (memory slot) organized in rows and columns, comprises line selection means (line decoder) for selecting a line or row of memory cells on the basis of a selection signal propagating over a word line linked up to all the memory cells of the row. Column selection means are also provided. These usually comprise control transistors controlled by a column decoder so as to select one or more columns of memory cells, depending on the length of the memory word.
A write and precharge circuit, as well as a read circuit are connected to the column decoder. Finally, a control circuit makes it possible to control these various elements. The read circuit conventionally comprises one or more amplifiers (depending on the length of the memory word) which are intended to measure the voltage difference between the two column metallizations (bit lines) to which the memory cells of a single column are connected.
The person skilled in the art is aware that, during a read phase, after the two column metallizations have been precharged to a predetermined voltage, for example VDD, a line of cells is selected by activating the corresponding word line. The control transistors situated at the bottom of columns are turned on simultaneously and the desired column or columns are selected by driving the column decoder. Upon activation of the corresponding word line, one of the metallizations of the selected column remains at the precharge voltage, while the voltage of the other metallization drops. Of the two metallizations, the one whose voltage drops depends on the 0 or 1 value of the bit stored in the relevant memory cell. The voltage difference at the terminals of the two metallizations increases as one of the storage transistors of the memory cell discharges the stray capacitance of the metallization.
The person skilled in the art is aware that the reading of this voltage difference can only be performed when the latter is greater than the offset voltage of the amplifier of the read circuit. This can occur only at the expiration of a certain delay Tr after the activation of the corresponding word line. Now, it is at present very difficult to determine in advance the delay Tr, as well as the value of the offset of the amplifier which depends on the particular technology, on the temperature of operation, and on the manufacturing procedures used.
One approach performs statistical simulations which require advanced statistical data and tools. Moreover, this simulation turns out to be ineffective upon a change of technology, or of format, or of any other characteristic of the memory.
The same holds for the characterization of the delay Tr which is performed at present by simulation. This is unwieldy to implement since it requires a model of the complete memory. Also, any subsequent modification of the structure of the memory may impair the results of the simulation. Finally, the delay Tr is generated by using delay lines, and these too have to be characterized.
Architectural approaches have currently finally been achieved, which are designed to operate in the most unfavorable cases. This is so notably with regards to the value of the delay Tr separating the instant of activation of the word line selection signal from the signal for activating the read amplifier.